1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the semiconductor device. Specifically, the present invention relates to a structure of a MISFET (metal insulator semiconductor field-effect transistor) and a method for fabricating the MISFET and, more particularly, relates to techniques for improving the driving power and reliability of a MISFET.
2. Description of Prior Art
In recent years, as the degree of integration, function and operation speed of semiconductor integrated circuit devices have been highly improved, there have been attempts to reduce a junction depth of an extension according to a scaling rule and, at the same time, to use, as a gate insulating film of a MISFET, a high dielectric constant film formed of a Hf based oxide, Al based oxide or the like, which has a relative dielectric constant of 10 or more, instead of an SiO2 based insulating film having a relative dielectric constant of about 4.
FIGS. 16A and 16B are cross-sectional views illustrating respective structures of known MISFETs using a high dielectric constant gate insulating film, respectively (see Ken Watanabe, HfSiON-CMOS technology for achieving high performance and high reliability, Semi. Forum Japan, 2005).
As shown in FIG. 16A, a gate electrode 105 is formed on a region of a well 102 surrounded by a STI (shallow trench isolation) 103. The region of the well 102 surrounded by the STI serves as an active region of a substrate 101. The gate electrode 105 is provided on the region with a high dielectric constant gate insulating film 104 interposed therebetween. An insulating sidewall 107 is formed on each side of the gate electrode 105. An extension region 110 is formed in part of the well 102 located under the insulating sidewall 107. A pocket region 111 is formed in part of the well 102 located under the extension region 110. Source/drain regions 112 are formed so that each of the source/drain regions 112 is provided in parts of the well 102 located at the external side to the extension region 110 and the pocket region 111 when viewed from the gate electrode 105.
A structure shown in FIG. 16B is different from a structure shown in FIG. 16A in that a sidewall 107 is formed on each side of a gate electrode 105 with an insulating offset sidewall 106 interposed therebetween. Thus, an overlapping amount of the gate electrode 105 and an extension region 110 can be optimized in a simple manner.